Semiconductor package

A semiconductor package comprising:

• a package substrate;
• a first semiconductor chip disposed on a package substrate, the first semiconductor chip including a first surface and a second surface opposite to each other;
• a first signal connection terminal disposed between the first surface of the first semiconductor chip and an upper surface of the package substrate, the first signal connection terminal electrically connecting the first semiconductor chip and the package substrate;
• a first dummy connection terminal interposed between the first surface of the first semiconductor chip and the upper surface of the package substrate, the first dummy connection terminal spaced apart from the first signal connection terminal;
• a second semiconductor chip overlying the second surface of the first semiconductor chip, the second semiconductor chip including a third surface and a fourth surface opposite to each other;
• a second signal connection terminal disposed between the third surface of the second semiconductor chip and the second surface of the first semiconductor chip, the second signal connection terminal electrically connecting the first semiconductor chip and the second semiconductor chip;
• and
• a second dummy connection terminal and a third dummy connection terminal which are disposed between the third surface of the second semiconductor chip and the second surface of the first semiconductor chip, the second dummy connection terminal and the third dummy connection terminal spaced apart from the second signal connection terminal,
• wherein at least a portion of the first dummy connection terminal and at least a portion of the second dummy connection terminal vertically overlap each other, and the first dummy connection terminal and the third dummy connection terminals does not vertically overlap each other;
• wherein a first area is a sum of an area in which the first signal connection terminal contacts the upper surface of the package substrate, and an area in which the first dummy connection terminal contacts the upper surface of the package substrate,
• wherein a second area is a sum of an area in which the second signal connection terminal contacts the second surface of the first semiconductor chip, an area in which the second dummy connection terminal contacts the second surface of the first semiconductor chip, and an area in which the third dummy connection terminal contacts the second surface of the first semiconductor chip,
• wherein the first area is larger than the second area.

A semiconductor package comprising:

• a package substrate including a substrate pad on an upper surface thereof;
• a first signal connection terminal electrically connected to the substrate pad;
• a first dummy connection terminal spaced apart from the substrate pad and the first signal connection terminal and disposed on the package substrate;
• a first semiconductor chip disposed on the first dummy connection terminal and the first signal connection terminal, the first semiconductor chip including a first via electrically connected to the first signal connection terminal;
• a second signal connection terminal connected to the first via and overlying the first semiconductor chip;
• a second dummy connection terminal spaced apart from the first via and the second signal connection terminal and overlying the first semiconductor chip;
• and
• a plurality of second semiconductor chips sequentially stacked on the second dummy connection terminal and the second signal connection terminal, each of the plurality of second semiconductor chips being electrically connected through a second via penetrating each of the plurality of second semiconductor chips,
• wherein a first area is a sum of an area in which the first signal connection terminal contacts the upper surface of the package substrate, and an area in which the first dummy connection terminal contacts the upper surface of the package substrate,
• wherein a second area is a sum of an area in which the second signal connection terminal contacts the first semiconductor chip, and an area in which the second dummy connection terminal contacts the first semiconductor chip, and
• wherein the first area is larger than the second area.