Device layer interconnects
AssigneeIntel Corporation
InventorsMark Bohr, Mauro Kobrinsky, Marni Nabors
Life of this patent
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Abstract
Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.
Claims25
An integrated circuit (IC) die, comprising:
- a device layer including a transistor array;
- a backside interconnect on a backside of the device layer;
- and
- a device layer interconnect in the device layer, electrically coupled to the backside interconnect, wherein the device layer interconnect is in conductive contact with a first source/drain region at a first surface of the device layer interconnect and a second source/drain region at a second, opposite surface of the device layer interconnect.
A method of fabricating an integrated circuit (IC) structure, comprising:
- forming a transistor array along a semiconductor fin;
- and
- forming a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.
A computing device, comprising:
- a circuit board;
- and
- an integrated circuit (IC) die coupled to the circuit board, wherein the IC die includes:
- a device layer including a transistor array along a semiconductor fin, and
- a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.
An integrated circuit (IC) package, comprising:
- a package substrate;
- and
- an IC die coupled to the package substrate, wherein the IC die includes a device layer, a backside interconnect on a backside of the device layer, and a device layer interconnect in the device layer, electrically coupled to the backside interconnect, wherein the device layer interconnect is in conductive contact with two distinct source/drain regions.
Dependencies are inferred from the claim text.