Patterning of dual metallization layers
AssigneeIntel Corporation
InventorJeremy Ecton
Life of this patent
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Abstract
Embodiments may relate to a semiconductor package that includes a routing trace coupled with a substrate. The routing trace may be linear on a side of the routing trace between the substrate and a top of the routing trace. The semiconductor package may further include a power trace coupled with the substrate. The power trace may be concave on a side of the power trace between the substrate and a top of the power trace. Other embodiments may be described and/or claimed.
Claims25
A semiconductor package comprising:
- a substrate;
- a routing trace coupled with the substrate, wherein a side of the routing trace between the substrate and a top of the routing trace is linearly sloped;
- and
- a power trace coupled with the substrate, wherein a side of the power trace between the substrate and a top of the power trace is concave.
A method of generating a substrate with a power trace and a routing trace positioned thereon, the method comprising:
- forming, via a semi-additive plating (SAP) technique, a first layer of the power trace and a first layer of the routing trace on the substrate;
- forming, via the SAP technique, a second layer of the power trace directly on the first layer of the power trace to form a power trace block;
- and
- etching, via a subtractive etch (SE) process, the power trace block to form the power trace.
A computing system comprising:
- a processor;
- a power supply;
- and
- a semiconductor package, wherein the semiconductor package includes:
- a substrate;
- a routing trace coupled with the substrate and communicatively coupled with the processor, wherein the routing trace is linear on a side of the routing trace between the substrate and a top of the routing trace and has a profile consistent with a semi-additive plating (SAP) technique;
- and
- a power trace coupled with the substrate and communicatively coupled with the power supply, wherein the power trace is concave on a side of the power trace between the substrate and a top of the power trace and has a profile consistent with a subtractive etch (SE) technique.
A semiconductor package comprising:
- a routing trace with a linearly sloped side face;
- and
- a power trace with a concave side face, wherein the power trace is made up of two separate layers of conductive material.
Dependencies are inferred from the claim text.