Semiconductor device with high-k gate dielectric layer

Abstract

Semiconductor device is provided. The semiconductor device includes a base substrate having a PMOS region and an NMOS region; a plurality gate structures formed on the base substrate, the gate structures including an interface layer formed on the base substrate, a high-K gate dielectric layer formed on the interface layer, a cap layer formed on the high-K gate dielectric layer and a metal layer formed over the high-K gate dielectric layer; an interlayer dielectric layer covering side surfaces of the gate structures formed over the base substrate; and source/drain doping regions formed in the base substrate at two sides of the gate structures. The gate structure is formed in an opening in the interlayer dielectric layer. The high-K gate dielectric layer is formed on side and bottom surfaces of the opening. The high-K dielectric layer contains additional oxygen ions diffused therein at a bottom portion.

Dependencies are inferred from the claim text.