Vertical transistor with reduced parasitic capacitance

An apparatus comprising:

• a substrate;
• a first fin and a second fin vertically disposed on the substrate, the first fin being adjacent to and parallel to the second fin;
• a first source/drain disposed on the substrate;
• a first dielectric spacer disposed on the first source/drain;
• a gate disposed on the first dielectric spacer and a portion of a vertical side of each of the first fin and the second fin;
• a trench adjacent to and parallel to the first fin and the second fin, the trench extending through a portion of the substrate, the trench including a top portion being narrower than a bottom portion;
• and
• a dielectric material disposed within the trench and pinching off the top portion of the trench to form an air gap spacer within the trench, the air gap spacer being parallel to and between the first fin and the second fin.

A computer usable program product comprising one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices, the stored program instructions comprising:

• program instructions to receive a semiconductor structure, the semiconductor structure including a substrate, the semiconductor structure further including a first fin and a second fin vertically disposed on the substrate;
• program instructions to form a first source/drain on the substrate;
• program instructions to form a first dielectric spacer on the first source/drain;
• program instructions to form a gate layer on the first dielectric spacer and a portion of a vertical side of each of the first fin and the second fin;
• program instructions to deposit a first sacrificial layer between the first fin and the second fin in contact with the gate layer;
• program instructions to recess the first sacrificial layer below an upper portion of the gate layer;
• program instructions to form a trench adjacent to and parallel to the first fin and the second fin;
• program instruction to deposit a second sacrificial layer in the trench and in contact with a portion of the gate layer;
• program instructions to form a second spacer on a portion of the second sacrificial layer in contact with a portion of the gate layer;
• program instructions to remove the second sacrificial layer;
• and
• program instructions to deposit a dielectric fill in a portion of the trench and pinching-off of the dielectric fill at a top portion of the trench to form an air gap spacer within the trench, the air gap spacer being adjacent to and parallel to the first fin and the second fin.