Semiconductor device with improved gate-source/drain metallization isolation

Abstract

A method of forming a semiconductor device such as a FinFET device includes forming a gate stack over a channel region of a semiconductor fin between spacer layers, recessing the gate stack and the spacer layers, and forming a gate conductor layer over both the recessed gate stack and the spacer layers. The gate conductor layer is adapted to inhibit etch damage to the spacer layers during a subsequent etching step used to form contact openings over source/drain regions of the fin. The resulting structure exhibits improved electrical isolation between gate and source/drain contacts.

Dependencies are inferred from the claim text.