Multiple patterning scheme integration with planarized cut patterning

A method for fabricating a semiconductor device integrating a multiple patterning scheme, comprising:

• forming a plurality of mandrels from a base structure;
• forming a plurality of non-mandrels including hard mask material having an etch property substantially similar to that of the plurality of mandrels;
• forming photo-sensitive material over the plurality of mandrels and the plurality of non-mandrels;
• and
• applying a double exposure scheme to the photo-sensitive material to create at least one mandrel cut pattern and at least one non-mandrel cut pattern, including performing a first lithography exposure to create the at least one mandrel cut pattern, and performing a second lithography exposure to create the at least one non-mandrel cut pattern.

A method for fabricating a semiconductor device integrating a multiple patterning scheme, comprising:

• forming a plurality of mandrels from a base structure, the base structure including a metal cap layer, a first dielectric layer formed on the metal cap layer, a hard mask layer formed on the IMD layer, and a second dielectric layer is formed on the hard mask layer, and wherein the mandrels include material from the second dielectric layer;
• forming a plurality of non-mandrels including hard mask material having an etch property substantially similar to that of the plurality of mandrels;
• forming photo-sensitive material over the plurality of mandrels and the plurality of non-mandrels;
• and
• applying an exposure scheme to the photo-sensitive material to create at least one mandrel cut pattern and at least one non-mandrel cut pattern.