Memory-testing methods for testing memory having error-correcting code

A memory-testing method adapted in a memory circuit, wherein the memory circuit comprises a first block and a second block, wherein the first block and the second block comprise a plurality of row addresses and a plurality of column addresses, wherein the memory-testing method comprises:

• selecting one of the row addresses to be a tested row according to selection logic;
• selecting one of the column addresses as a tested column according to the selection logic;
• selecting a plurality of sampled column addresses on the tested row according to a sampling procedure;
• selecting a plurality of sampled row addresses on the tested column according to the sampling procedure;
• simultaneously executing a read operation on the sampled column addresses on the tested row of the first block and the second block;
• simultaneously executing the read operation on the sampled row addresses on the tested column of the first block and the second block;
• determining whether the read fail rate of the read operation executed on the memory circuit is 0;
• when the read fail ratio of the memory circuit is not 0, determining whether the read fail ratio of the first block and/or the second block exceeds a predetermined ratio;
• and
• when the read fail ratio of the first block and/or the second block exceeds the predetermined ratio, marking the first block and/or the second block as a solid input/output fail.