US 2019/0378585 A1 · SEMICONDUCTOR DEVICE

Abstract

A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.

Claims7

Dependent claims

(canceled)

A semiconductor device comprising:

a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor;
and
a ninth transistor,
wherein:
the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor have a same conductivity type;
one of a source and a drain of the first transistor is electrically connected to a first wiring;
the other of the source and the drain of the first transistor is electrically connected to a second wiring;
one of a source and a drain of the second transistor is electrically connected to the second wiring;
the other of the source and the drain of the second transistor is electrically connected to a third wiring;
one of a source and a drain of the third transistor is electrically connected to a fourth wiring;
the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;
one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor;
one of a source and a drain of the sixth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor;
a gate of the sixth transistor is electrically connected to the gate of the first transistor;
a gate of the seventh transistor is electrically connected to the other of the source and the drain of the third transistor;
one of a source and a drain of the eighth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor;
a gate of the eighth transistor is electrically connected to a gate of the first transistor,
the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring;
a first conductive layer is electrically connected to a third conductive layer through a second conductive layer;
the first conductive layer is configured to be the gate of the first transistor;
the third conductive layer is configured to be a gate of the third transistor;
the second conductive layer comprises a region in contact with top of an insulating film configured to be a gate insulating film of the first transistor, and
the second wiring is configured to transmit a signal being output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor.

31 more elements

A semiconductor device comprising:

a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor;
and
a ninth transistor,
wherein:
the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor have a same conductivity type;
one of a source and a drain of the first transistor is electrically connected to a first wiring;
the other of the source and the drain of the first transistor is electrically connected to a second wiring;
one of a source and a drain of the second transistor is electrically connected to the second wiring;
the other of the source and the drain of the second transistor is electrically connected to a third wiring;
one of a source and a drain of the third transistor is electrically connected to a fourth wiring;
the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;
one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor;
one of a source and a drain of the sixth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor;
a gate of the sixth transistor is electrically connected to the gate of the first transistor;
a gate of the seventh transistor is electrically connected to the other of the source and the drain of the third transistor;
one of a source and a drain of the eighth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor;
a gate of the eighth transistor is electrically connected to a gate of the first transistor;
the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring;
a first conductive layer is electrically connected to a third conductive layer through a second conductive layer;
the first conductive layer is configured to be the gate of the first transistor;
the third conductive layer is configured to be a gate of the third transistor;
the second conductive layer comprises a region in contact with top of an insulating film configured to be a gate insulating film of the first transistor;
the second wiring is configured to transmit a signal being output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor, and
a ratio of a channel width of the first transistor to a channel length of the first transistor is larger than a ratio of a channel width of the first transistor to a channel length of the third transistor.

32 more elements

A semiconductor device comprising:

a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor;
and
a ninth transistor,
wherein:
the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor have a same conductivity type;
one of a source and a drain of the first transistor is electrically connected to a first wiring;
the other of the source and the drain of the first transistor is electrically connected to a second wiring;
one of a source and a drain of the second transistor is electrically connected to the second wiring;
the other of the source and the drain of the second transistor is electrically connected to a third wiring;
one of a source and a drain of the third transistor is electrically connected to a fourth wiring;
the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;
one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor;
one of a source and a drain of the sixth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor;
a gate of the sixth transistor is electrically connected to the gate of the first transistor;
a gate of the seventh transistor is electrically connected to the other of the source and the drain of the third transistor;
one of a source and a drain of the eighth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor;
a gate of the eighth transistor is electrically connected to a gate of the first transistor;
the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring;
a first conductive layer is electrically connected to a third conductive layer through a second conductive layer;
the first conductive layer is configured to be the gate of the first transistor;
the third conductive layer is configured to be a gate of the third transistor;
the second conductive layer comprises a region in contact with top of an insulating film configured to be a gate insulating film of the first transistor;
the second wiring is configured to transmit a signal being output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor, and
the first conductive layer is constantly electrically connected to the third conductive layer.

32 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/547,976Filed 22 Aug 2019

Priority

JP 2011-2229907 Oct 2011

Published

12 Dec 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 19/184
In combination with semiconductor elements, e.g. bipolar transistors, diodes: with field-effect transistors, e.g. MOS-FET
H10D 86/421
Characterised by multiple TFTs: having a particular composition, shape or crystalline structure of the active layer
H10D 86/423
Having a particular composition, shape or crystalline structure of the active layer: comprising semiconductor materials not belonging to the Group…
H10D 86/441
Characterised by multiple TFTs: interconnections, e.g. scanning lines

Family

Application13/632,564Continuation · filed 1 Oct 2012

Application16/017,181Continuation · filed 25 Jun 2018

Application16/547,976Continuation

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US 2013/0088468 A1Published application

US 2018/0308558 A1Published application

US 2019/0378585 A1This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims7