Cmos anti-fuse cell

A method of operating a multi-time programmable (MTP) anti-fuse apparatus having an N− well, a select gate (SG) transistor formed on the N− well, the SG transistor having a SG P+ drain diffusion coupled to a bit line and a SG P+ source diffusion, the apparatus also having a plurality of one-time programmable (OTP) anti-fuse cells formed in series on the N− well, wherein each anti-fuse cell includes an oxide layer deposited on the N− well, a control gate deposited on the oxide layer, a drain P+ diffusion deposited in the N− well and forming an overlapping region with the oxide layer, and a source P+ diffusion deposited in the N− well, and wherein the drain P+ diffusion of a first anti-fuse cell is coupled to the SG P+ source diffusion, and the source P+ diffusions of each remaining anti-fuse cell are coupled to the drain P+ diffusions of adjacent anti-fuse cells, the method comprising:

• applying a first voltage to the bit line;
• applying a second voltage to a gate terminal of the control gate;
• applying a third voltage to the control gates of all anti-fuse cells between the select gate and a selected anti-fuse cell;
• and
• applying a fourth voltage to the control gate of the selected anti-fuse cell.

A multi-time programmable (MTP) anti-fuse apparatus, comprising:

• a P− well;
• a select gate (SG) transistor formed on the P− well and having a SG N+ drain diffusion coupled to a bit line and a SG N+ source diffusion;
• a plurality of one-time programmable (OTP) anti-fuse cells formed in series on the P− well, wherein each anti-fuse cell includes an oxide layer deposited on the P− well, a control gate deposited on the oxide layer, a drain N+ diffusion deposited in the P− well and forming an overlapping region with the oxide layer, and a source N+ diffusion deposited in the P− well;
• wherein the drain N+ diffusion of a first anti-fuse cell is coupled to the SG N+ source diffusion, and the source N+ diffusions of each remaining anti-fuse cell are coupled to the drain N+ diffusions of adjacent anti-fuse cells;
• wherein a selected anti-fuse cell is programmed by enabling the select gate and all anti-fuse cells between the select gate and the selected anti-fuse cell, and applying programming conditions to the selected anti-fuse cell;
• and
• wherein the anti-fuse apparatus is reprogrammed when a second selected anti-fuse cell that is located between the select gate and the selected anti-fuse cell is programmed by enabling the select gate and all anti-fuse cells between the select gate and the second selected anti-fuse cell, and applying programming conditions to the second selected anti-fuse cell.