US 2019/0378575 A1 · METHOD AND APPARATUS FOR PUF GENERATOR CHARACTERIZATION

Abstract

Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a testing method for physical unclonable function (PUF) generator includes: verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array; determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the preconfigured logical states; if the first number of first bit cells is less than a first predetermined number, generating a first map under a first set of operation conditions using the PUF generator and a masking circuit, wherein the first map comprises at least one stable bit cells and at least one unstable bit cell; generating a second map under a second set of operation conditions using the PUF generator and the masking circuit, wherein the second map comprises at least one stable bit cells and at least one unstable bit cell; determining a second number of second bit cells, wherein the second bit cells are stable in the first map and unstable in the second map using a Built-in Self Test (BIST) engine; if the second number of second bit cells is determined to be zero, determining a third number of third bit cells using the BIST engine, wherein the third bit cells are stable in the first map and stable in the second map; and if the third number of third bit cells are greater than a second preconfigured number, the PUF generator is determined as a qualified PUF generator.

Claims20

Dependent claims

A testing method for physical unclonable function (PUF) generator comprising:

verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array,
determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the preconfigured logical states;
if the first number of first bit cells is less than a first predetermined number, generating a first map under a first set of operation conditions using the PUF generator and a masking circuit, wherein the first map comprises at least one stable bit cells and at least one unstable bit cell;
generating a second map under a second set of operation conditions using the PUF generator and the masking circuit, wherein the second map comprises at least one stable bit cells and at least one unstable bit cell;
determining a second number of second bit cells, wherein the second bit cells are stable in the first map and unstable in the second map using a Built-in Self Test (BIST) engine;
if the second number of second bit cells is determined to be zero, determining a third number of third bit cells using the BIST engine, wherein the third bit cells are stable in the first map and stable in the second map;
and
if the third number of third bit cells are greater than a second preconfigured number, the PUF generator is determined as a qualified PUF generator.

5 more elements

A physical unclonable function (PUF) generator comprising:

a PUF cell array comprising a plurality of bit cells, wherein the plurality of bit cells each provides a logical state;
a controller coupled to the PUF cell array, wherein the controller is configured to provide a first set and a second set of operation conditions to the PUF cell array;
a masking circuit configured to determine a first map and a second map, wherein the first and second maps determined under the first and second set of operation conditions, respectively, each comprises a plurality of logical states of the plurality of bit cells in the PUF cell array, wherein wherein the first and second maps each comprises at least one stable bit cells and at least one unstable bit cell;
and
a Built-In Self Test (BIST) engine, configured to determine a first number of first bit cells and a second number of second bit cells, wherein the first bit cells are stable in the first map and unstable in the second map, wherein the second bit cells are stable in the first map and stable in the second map.

2 more elements

A physical unclonable function (PUF) generator comprising:

a PUF cell array comprising a plurality of bit cells, wherein the plurality of bit cells each comprises two cross-coupled inverters;
at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state;
a controller coupled to the PUF cell array, wherein the controller comprising a delay circuit is configured to provide a first set and a second set of operation conditions to the PUF cell array;
a masking circuit configured to determine a first map and a second map, wherein the first and second maps determined under the first and second set of operation conditions, respectively, each comprises a plurality of logical states of the plurality of bit cells in the PUF cell array, wherein wherein the first and second maps each comprises at least one stable bit cells and at least one unstable bit cell;
and
a Built-In Self Test (BIST) engine, configured to determine a first number of first bit cells and a second number of second bit cells, wherein the first bit cells are stable in the first map and unstable in the second map, wherein the second bit cells are stable in the first map and stable in the second map.

3 more elements

Dependencies are inferred from the claim text.

Method and apparatus for puf generator characterization

Life of this patent

Method and apparatus for puf generator characterization

Life of this patent

Abstract

Claims20