Reduced current memory device
AssigneeRambus Inc.
InventorsDeepak Chandra SEKAR, Brent S. HAUKNESS, Bruce L. BATEMAN
Life of this patent
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Abstract
A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.
Claims20
A memory device, comprising:
- a local bit line electrically coupled to a plurality of memory cells;
- and
- a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively;
- wherein the first path is active and the second path is in an off state in at least one of a set operation or a forming operation;
- and
- wherein the second path is active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.
A memory device, comprising:
- a global bit line;
- a local bit line coupled to a plurality of memory cells;
- and
- a coupling circuit configured to couple the global bit line to the local bit line through first and second selectable parallel impedance paths, such that a first coupling impedance is selectable for at least one of a set operation, a reset operation, or a forming operation, and a second coupling impedance is selectable for at least a different one other of the set operation, the reset operation, or the forming operation,
- wherein the second selectable impedance path has a second impedance lower than a first impedance of the first selectable impedance path.
A non-volatile memory device, comprising:
- a memory element;
- and
- a selecting element having a first impedance path electrically coupled to the memory element in response to a first control signal and having a second impedance path parallel to the first impedance path coupled to the memory element only in response to a second control signal,
- wherein the second impedance path has a second impedance lower than a first impedance of the first impedance path.
Dependencies are inferred from the claim text.