Techniques for programming multi-level self-selecting memory cell

A method, comprising:

• identifying a desired logic state for a self-selecting memory cell that is configured to store more than two logic states;
• identifying a current logic state of the self-selecting memory cell;
• selecting a programming pulse based at least in part on the desired logic state and the current logic state;
• applying the programming pulse to the self-selecting memory cell;
• and
• storing the desired logic state in the self-selecting memory cell based at least in part on applying the programming pulse.

A memory apparatus, comprising:

• a word line;
• a bit line;
• a self-selecting memory cell having a bottom surface coupled with the word line and a top surface opposite the bottom surface, the top surface coupled with the bit line, the self-selecting memory cell comprising a tapered profile between the bottom surface and the top surface;
• and
• a controller operable to:
• identify a first logic state for the self-selecting memory cell configured to store more than two logic states;
• apply a first pulse with a first polarity to the self-selecting memory cell to program the self-selecting memory cell with a second logic state different than the first logic state;
• apply a second pulse with a second polarity to the self-selecting memory cell to program the self-selecting memory cell with the first logic state, wherein the second polarity is different than the first polarity and the first amplitude is greater than the second amplitude, wherein the first logic state is an intermediate state;
• and
• store the first logic state in the self-selecting memory cell based at least in part on applying the first pulse with the first polarity and the second pulse with the second polarity.