Memory device for compensating for current of off cells and operating method thereof

A memory device comprising:

• a memory cell array comprising a plurality of memory cells connected to intersections of a plurality of local word lines connected to a plurality of global word lines, and a plurality of local bit lines connected to a plurality of global bit lines;
• a local word line select transistor disposed on a selected local word line from among the plurality of local word lines, the selected local word line coupled to a selected memory cell of the plurality of memory cells, the local word line select transistor configured to selectively form an electrical flow path between the selected memory cell and a selected global word line from among the plurality of global word lines;
• and
• a leakage current compensation circuit coupled to the local word line select transistor and configured to compensate for a first current value representing a sum of leakage currents generated by unselected memory cells coupled to the selected local word line, in a read operation mode of the memory device.

A memory device comprising:

• a memory cell array comprising a plurality of memory cells coupled to intersections of a plurality of local word lines coupled to a plurality of global word lines, and a plurality of local bit lines coupled to a plurality of global bit lines;
• a global word line select transistor disposed on a selected global word line from among the plurality of global word lines, the selected global word line connected to a selected local word line from among the plurality of local word lines, the selected local word line connected to a selected memory cell of the plurality of memory cells, the global word line select transistor configured to selectively form an electrical flow path between the selected local word line and a read/write circuit of the memory device;
• and
• a leakage current compensation circuit coupled to the global word line select transistor and configured to compensate for a first current value generated by off cells from among the plurality of memory cells in a read operation mode of the memory device, the off cells connected to the selected local word line of the plurality of memory cells.