Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein
AssigneeR&D 3 LLC
InventorRavindraraj Ramaraju
Life of this patent
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Abstract
The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.
Claims21
1-20. (canceled)
A circuit device comprising:
- a first transistor having a first electrode coupled to a first supply voltage, a control electrode coupled to an input signal, and a second electrode;
- a second transistor having a first electrode coupled to the second electrode of the first transistor, a control electrode coupled to a control signal, and a second electrode coupled to a signal node, wherein an assertion of the control electrode of the second transistor causes a voltage on the signal node;
- a delay element having:
- an input coupled to the signal node, and
- an output, wherein the delay element is configured to:
- in response to an assertion of the control electrode of the second transistor, effect a voltage transition at a variable rate corresponding to a voltage of the input signal, and
- determine a value of the input signal based upon a time-to-transition measurement of the output.
A method for determining a signal value in an integrated circuit, said method comprising:
- enabling a first circuit to couple a signal value onto a signal node;
- effecting, using a delay element, a voltage transition of an output of the delay element at a variable rate corresponding to a voltage of the signal value, wherein the delay element has an input coupled to the signal node;
- and
- determining, the signal value based upon a time-to-transition measurement of the output of the delay element.
Dependencies are inferred from the claim text.