Semiconductor memory device

A semiconductor memory device, comprising:

• at least one memory cell array, comprising a plurality of memory cells arranged along a plurality of word lines and a plurality of bit lines orthogonal to one another, the plurality of bit lines comprising a plurality of first bit lines and a plurality of second bit lines;
• a plurality of switching elements, for connecting or disconnecting each of the memory cells arranged along a corresponding word line of the word lines to or from a corresponding first bit line of the first bit lines or a corresponding second bit line of the second bit lines, arranged along the corresponding word line of the word lines, in accordance with an activated or inactive state of the corresponding word line of the word lines;
• a plurality of sense amplifiers, each connected to one of the plurality of first bit lines and one of the plurality of second bit lines;
• and
• a control circuit, for activating or deactivating the word lines and the sense amplifiers,
• wherein at least three memory cells comprising first to third memory cells among the plurality of memory cells are arranged along each of the first bit lines and each of the second bit lines,
• wherein the first and the second memory cells are each connected to or disconnected from the corresponding first bit line by first and second switching elements among the plurality of switching elements, in accordance with an active or inactive state of first and second word lines among the plurality of word lines,
• wherein the third memory cell is connected to or disconnected from the corresponding second bit line by a third switching element among the plurality of switching elements, in accordance with an active or inactive state of a third word line among the plurality of word lines,
• wherein the first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third memory cell stores a third bit value, and
• wherein the control circuit activates the first to third word lines and then activates the corresponding sense amplifier so that a logical AND operation or a logical OR operation specified by one of the first to third bit values is performed on remaining two of the first to third bit values.

A method of manufacturing a semiconductor memory device, where the semiconductor memory device comprises at least one memory cell array comprising a plurality of memory cells arranged alone a plurality of bit lines and a plurality of word lines orthogonal to each other, the method comprising steps of:

• forming the plurality of bit lines;
• forming the plurality of word lines;
• forming the plurality of memory cells;
• forming a plurality of switching elements connecting or disconnecting each of the memory cells arranged along a corresponding word line of the word lines to or from a corresponding bit line of the bit lines in accordance with an active state or an inactive state of the corresponding word line;
• forming a plurality of sense amplifiers connected to the plurality of bit lines, respectively;
• and
• forming a control circuit for activating or deactivating each of the word lines and the sense amplifiers,
• wherein at least four memory cells comprising first to fourth memory cells among the plurality of memory cells are arranged along a corresponding bit line of the bit lines,
• wherein the first to fourth memory cells are each connected to or disconnected from one bit line by first to fourth switching elements among the plurality of switching elements, in accordance with active or inactive states of first to fourth word lines among the plurality of word lines,
• wherein the first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value, and
• wherein the control circuit activates the third and fourth word lines, then deactivates the third and fourth word lines, subsequently
• activates the first and second word lines, and then activates the corresponding sense amplifier so that
• a logical AND operation or a logical OR operation specified by the third bit value is performed on the first and second bit values.

A data processing method using a semiconductor memory device,

• said semiconductor memory device, comprising:
• at least one memory cell array, comprising a plurality of memory cells arranged along a plurality of word lines and a plurality of bit lines orthogonal to one another,
• a plurality of switching elements, for connecting or disconnecting each of the memory cells arranged along a corresponding word line of the word lines to or from a corresponding bit line of the bit lines in accordance with an active or inactive state of the corresponding word line;
• a plurality of sense amplifiers, connected to the plurality of bit lines, respectively;
• and
• a control circuit, for activating or deactivating the word lines and the sense amplifiers,
• wherein at least four memory cells comprising first to fourth memory cells among the plurality of memory cells are arranged along a corresponding bit line of the bit lines,
• wherein the first to fourth memory cells are each connected to or disconnected from one bit line by first to fourth switching elements among the plurality of switching elements, in accordance with an active or inactive state of first to fourth word lines among the plurality of word lines,
• wherein the first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value, and
• wherein the control circuit activates the third and fourth word lines, then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the corresponding sense amplifiers so that a logical AND operation or a logical OR operation specified by the third bit value is performed on the first and second bit values;
• storing a record comprising a plurality of bit values indicating at least one attribute in a plurality of memory cells arranged along the bit line, for each of the bit lines.