US 2019/0378556 A1 · SEMICONDUCTOR MEMORY DEVICE, POWER DECOUPLING CAPACITOR ARRAY THEREOF, AND MEMORY SYSTEM HAVING THE SAME

Abstract

A semiconductor memory device, a power decoupling capacitor array thereof, and a memory system including the same are disclosed. The semiconductor memory device includes a memory cell array, a peripheral circuit, and a plurality of power decoupling capacitor arrays. The memory cell array includes a plurality of memory cells, and each of the plurality of memory cells includes a cell capacitor. Each of the plurality of power decoupling capacitor arrays includes m×n power decoupling capacitor sub arrays in an m×n matrix form. Each of the m×n power decoupling capacitor sub arrays includes a plurality of power decoupling capacitors, and each of the plurality of power decoupling capacitors has the same structure as the cell capacitor and the plurality of power decoupling capacitors are connected in parallel. A first voltage and a second voltage, which are different from each other, are applied to two of the power decoupling capacitor sub arrays arranged adjacent in a first direction and two of the power decoupling capacitor sub arrays a second direction.

Claims20

Dependent claims

A semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cells, each of the plurality of memory cells comprising a cell capacitor;
a peripheral circuit configured to input data applied from an external source to the memory cell array or output data from the memory cell array to the external source;
and
a plurality of power decoupling capacitor arrays configured to reduce power noise occurring between a first voltage and a second voltage, which are different from each other,
wherein each of the plurality of power decoupling capacitor arrays comprises m×n power decoupling capacitor sub arrays in an m×n matrix form,
wherein each of the m×n power decoupling capacitor sub arrays comprises a plurality of power decoupling capacitors,
wherein each of the plurality of power decoupling capacitors has a same structure as the cell capacitor and the m×n power decoupling capacitors are connected in parallel,
wherein the first voltage and the second voltage are applied to two of the plurality of power decoupling capacitor sub arrays arranged adjacent in a first direction and two of the m×n power decoupling capacitor sub arrays arranged adjacent in a second direction, wherein
wherein m and n are respective integer values greater than or equal to two.

6 more elements

A memory system comprising:

a memory controller;
and
a memory configured to input and output data in response to control signals from the memory controller,
wherein the memory comprises at least one semiconductor memory device,
wherein the at least one semiconductor memory device comprises
a memory cell array comprising a plurality of memory cells, each of the plurality of memory cells comprising a cell capacitor,
a peripheral circuit configured to input data from the memory controller to the memory cell array, or output data from the memory cell array to the memory controller, and
a plurality of power decoupling capacitor arrays configured to reduce power noise between a first voltage and a second voltage, which are different from each other,
wherein each of the plurality of power decoupling capacitor arrays comprises m×n power decoupling capacitor sub arrays arranged in an m×n matrix form,
wherein each of the m×n power decoupling capacitor sub arrays comprises a plurality of power decoupling capacitors,
wherein each of the plurality of power decoupling capacitors has substantially a same structure as the cell capacitor and the plurality of power decoupling capacitors are connected in parallel,
wherein the first voltage and the second voltage are applied to two of the m×n power decoupling capacitor sub arrays arranged adjacent in a first direction, and two of the m×n power decoupling capacitor sub arrays arranged adjacent in a second direction, and
wherein m and n are respective integer values greater than or equal to two.

10 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device, power decoupling capacitor array thereof, and memory system having the same

Life of this patent

Semiconductor memory device, power decoupling capacitor array thereof, and memory system having the same

Life of this patent

Abstract

Claims20