High-Speed Data Transfer Periods for Thyristor Memory Cell Arrays

In an activation cycle transferring data to and/or from a random access memory cell array, the activation cycle having a Read operation in which data from a selected row of memory cells in the memory cell array is read and latched into a buffer, a Burst operation in which the latched memory cell row data is transferred from the random access memory cell array to an external location or external data is transferred into the random access memory cell array and latched in the buffer, and a Write-Recovery and Pre-charge operation in which the random access memory array is prepared for another activation cycle, an improved method of transferring data to and from the selected row comprising:

• during the Burst operation, setting all memory cells in the selected row in a first logic state;
• and
• during the Write-Recovery and Pre-charge operation, writing a second logic state into memory cells in the selected row of memory cells corresponding to the latched data in the second logic state;
• whereby time constraints in writing data back from the buffer into the selected row of memory cells are reduced.

In an array of memory cells interconnected by a plurality of word lines and bit lines, a method of transferring data into and out of the array of memory cells, comprising:

• latching a plurality of first data bits read from the memory cells connected to a selected word line;
• moving the plurality of first data bits to a location external to the array of memory cells or a plurality of second data bits from a location external to the memory cell array and latching the plurality of second data bits for the memory cells connected to the selected word line, and simultaneously writing a first logic state into all the memory cells connected to the selected word line;
• then writing latched second logic states into corresponding memory cells connected to the selected word line;
• whereby the transfer of data bits can be performed at high speed.