Memory device in which locations of registers storing fail addresses are merged

A memory device comprising:

• a bank including first memory cells connected to a first word line and second memory cells connected to a second word line;
• a first row decoder configured to select the first memory cells by transmitting a first row selection signal in a first direction through the first word line;
• and
• a second row decoder configured to select the second memory cells by transmitting a second row selection signal in a second direction opposite to the first direction through the second word line,
• wherein the first row decoder includes:
• a first register configured to store a first fail row address of the first memory cells;
• and
• a second register configured to store a second fail row address of the second memory cells.

A memory device comprising:

• a first bank including first memory cells connected to a first column selection line, first input/output lines of the first memory cells being arranged in the first bank;
• a second bank including second memory cells connected to a second column selection line, second input/output lines of the second memory cells being arranged in the second bank;
• a first column decoder configured to select the first memory cells by transmitting a first column selection signal in a first direction through a first column selection line and to perform first data input/output on the first memory cells through the first input/output lines;
• and
• a second column decoder configured to select the second memory cells by transmitting a second column selection signal in a second direction opposite to the first direction through a second column selection line and to perform second data input/output on the second memory cells through the second input/output lines,
• wherein the first column decoder includes:
• a first register configured to store a first fail column address of the first memory cells in the first bank;
• and
• a second register configured to store a second fail column address of the second memory cells in the second bank.