Circuitry for tracking bias voltage behavior

An integrated circuit, comprising:

• dummy wordline driver circuitry coupled to a dummy wordline;
• dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline;
• and
• dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry, wherein the dummy wordline tracking circuitry has one or more variable capacitors that are coupled between the dummy wordline and a variable voltage source;
• wherein the one or more variable capacitors are used for switching between multiple capacitance values, and wherein the switching is performed dynamically.

An integrated circuit, comprising:

• dummy wordline driver circuitry coupled to a dummy wordline;
• dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline;
• and
• dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry, wherein the dummy wordline tracking circuitry has one or more variable capacitors that are coupled between the dummy wordline and a variable voltage source;
• wherein the one or more variable capacitors have a first terminal that is coupled to the dummy wordline;
• wherein the one or more variable capacitors have a second terminal that is coupled to the variable voltage source to receive a control signal that switches between a first state and a second state that is different than the first state.

An integrated circuit, comprising:

• dummy wordline driver circuitry coupled to a dummy wordline;
• dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline;
• and
• dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry, wherein the dummy wordline tracking circuitry has one or more variable capacitors that are coupled between the dummy wordline and a variable voltage source;
• wherein the one or more variable capacitors are implemented with a transistor that is coupled together to operate as a capacitor;
• wherein the one or more variable capacitors have a first terminal that is a gate of the transistor.

An integrated circuit, comprising:

• dummy bitline pulldown circuitry coupled to a dummy bitline;
• global timing pulse reset circuitry coupled between a dummy wordline and the dummy bitline;
• and
• dummy bitline tracking circuitry coupled to the dummy bitline between the dummy bitline pulldown circuitry and the global timing pulse reset circuitry, wherein the dummy bitline tracking circuitry has one or more variable capacitors that are coupled between the dummy bitline and a variable voltage source comprising a variable source voltage supply.

An integrated circuit, comprising:

• dummy bitline pulldown circuitry coupled to a dummy bitline;
• global timing pulse reset circuitry coupled between a dummy wordline and the dummy bitline;
• and
• dummy bitline tracking circuitry coupled to the dummy bitline between the dummy bitline pulldown circuitry and the global timing pulse reset circuitry, wherein the dummy bitline tracking circuitry has one or more variable capacitors that are coupled between the dummy bitline and a variable voltage source;
• wherein the one or more variable capacitors are used for dynamically switching between multiple capacitance values at any time within a memory operation cycle.

An integrated circuit, comprising:

• dummy bitline pulldown circuitry coupled to a dummy bitline;
• global timing pulse reset circuitry coupled between a dummy wordline and the dummy bitline;
• and
• dummy bitline tracking circuitry coupled to the dummy bitline between the dummy bitline pulldown circuitry and the global timing pulse reset circuitry, wherein the dummy bitline tracking circuitry has one or more variable capacitors that are coupled between the dummy bitline and a variable voltage source;
• wherein the one or more variable capacitors are implemented with a transistor that is coupled together to operate as a capacitor, wherein the one or more variable capacitors have a first terminal that is a gate of the transistor, and wherein the one or more variable capacitors have a second terminal that is a source/drain connection of the transistor.

An integrated circuit, comprising:

• dummy wordline driver circuitry coupled to a dummy wordline;
• dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline;
• global timing pulse reset circuitry coupled between the dummy wordline and the dummy bitline;
• dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry, wherein the dummy wordline tracking circuitry has at least one first variable capacitor that is coupled between the dummy wordline and a first variable voltage source;
• and
• dummy bitline tracking circuitry coupled to the dummy bitline between the dummy bitline pulldown circuitry and the global timing pulse reset circuitry, wherein the dummy bitline tracking circuitry has at least one second variable capacitor that is coupled between the dummy bitline and a second variable voltage source;
• wherein the first variable voltage source is a variable source voltage supply.

An integrated circuit, comprising:

• dummy wordline driver circuitry coupled to a dummy wordline;
• dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline;
• global timing pulse reset circuitry coupled between the dummy wordline and the dummy bitline;
• dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry, wherein the dummy wordline tracking circuitry has at least one first variable capacitor that is coupled between the dummy wordline and a first variable voltage source;
• and
• dummy bitline tracking circuitry coupled to the dummy bitline between the dummy bitline pulldown circuitry and the global timing pulse reset circuitry, wherein the dummy bitline tracking circuitry has at least one second variable capacitor that is coupled between the dummy bitline and a second variable voltage source;
• wherein the second variable voltage source is a variable source voltage supply.