Goa circuit and oled display device

A gate driver on array (GOA) circuit, which comprises:

• a plurality of cascaded GOA units, with each GOA unit comprising:
• a scan signal output module and an emitting signal output module electrically connected to the scan signal output module;
• for a positive integer n, except the first GOA unit, in the n-th GOA unit:
• the scan signal output module, receiving an m-th clock signal, an (m+1)-th clock signal, and a scan signal of the (n−1)-th GOA unit, for outputting a scan signal of n-th GOA unit to sub-pixels of n-th row and the emitting signal output module of the n-th GOA unit according to the m-th clock signal under the control of the scan signal of the (n−1)-th GOA unit;
• the emitting signal output module, receiving the scan signal outputted by the scan signal output module of the n-th GOA unit, for outputting an emitting signal of the n-th GOA unit to the sub-pixels of n-th row;
• during a frame period, the scan signal of each GOA unit comprising at least two low voltage pulses, the emitting signal of each GOA unit having a duration of outputting high voltage longer than twice the pulse cycle of the m-th clock signal, and the m-th clock signal and the (m+1)-th clock signal having opposite phases;
• wherein the scan signal output module comprising:
• a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, a ninth TFT, a tenth TFT, an eleventh TFT, a twelfth TFT, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;
• the first TFT having a gate receiving a constant low voltage, a source electrically connected to a drain of the second TFT, and a drain electrically connected to a first node of the n-th GOA unit;
• the second TFT having a gate and a source, both receiving the scan signal of the (n−1)-th GOA unit;
• the third TFT having a gate receiving the constant low voltage, a source electrically connected to the source of the second TFT, and a drain electrically connected to a gate of the fifth TFT;
• the fourth TFT having a gate receiving the constant low voltage, a source electrically connected to the first node of the n-th GOA unit, and a drain electrically connected to a source of the sixth TFT;
• the fifth TFT having a source electrically connected to a second node of the n-th GOA unit, and a drain receiving a constant high voltage;
• the sixth TFT having a gate electrically connected to the second node of the n-th GOA unit, and a drain receiving a constant high voltage;
• the seventh TFT having a gate electrically connected to the drain of the third TFT, a source electrically connected to a drain of the eighth TFT, and a drain receiving the constant high voltage;
• the eighth TFT having a gate and a source, both receiving the m-th clock signal;
• the ninth TFT having a gate receiving the (m+1)-th clock signal, a source electrically connected to a drain of the tenth TFT, and a drain electrically connected to the second node of the n-th GOA unit;
• the tenth TFT having a gate electrically connected to the drain of the eighth TFT, and a source receiving the (m+1)-th clock signal;
• the eleventh TFT having a gate electrically connected to the second node of the GOA unit, a source electrically connected to a drain of the twelfth TFT, and a drain receiving the constant high voltage;
• the twelfth TFT having a gate electrically connected to the first node of the GOA unit, a source receiving the m-th clock signal, and a drain outputting the scan signal of the n-th GOA unit;
• the first capacitor having a first end electrically connected to the source of the sixth TFT, and a second end receiving the constant high voltage;
• the second capacitor having a first end electrically connected to the first node of the GOA unit, and a second end electrically connected to the drain of the twelfth TFT;
• the third capacitor having a first end electrically connected to the second node of the GOA unit, and a second end receiving the constant high voltage;
• the fourth capacitor having a first end electrically connected to the drain of the eighth TFT, and a second end receiving the constant high voltage;
• wherein the emitting signal output module comprising:
• a thirteenth TFT, a fourteenth TFT, a fifteenth TFT, a sixteenth TFT, and a fifth capacitor;
• the thirteenth TFT having a gate receiving the scan signal of the n-th GOA unit, a source receiving the constant high voltage, and a drain electrically connected to a source of the fourteenth TFT;
• the fourteenth TFT having a gate receiving the emitting signal of the n-th GOA unit, and a drain receiving the constant low voltage;
• the fifteenth TFT having a gate receiving the emitting signal of the n-th GOA unit, a source receiving the constant high voltage, and a drain outputting the emitting signal of the n-th GOA unit;
• the sixteenth TFT having a gate electrically connected to the drain of the thirteen TFT, a source electrically connected to the drain of the fifteenth TFT, and a drain receiving the constant low voltage;
• the fifth capacitor having a first end electrically connected to the drain of the thirteenth TFT, and a second end receiving the m-th clock signal;
• comprising two clock signals;
• a first clock signal and a second clock signal;
• when the m-th clock signal being the second clock signal, the (m+1)-th clock signal being the first clock signal;
• wherein in the first GOA unit, both the gate and the source of the second TFT receiving a circuit start signal.