Semiconductor package metal shadowing checks

A system for checking metal coverage in a laminate structure, the system having a processor coupled to a memory, the processor configured to:

• receive a semiconductor package design comprising a plurality of layers, a power shape, and a signal line;
• compress the plurality of layers into a three-dimensional (3-D) array, wherein each cell of the 3-D array corresponds to a unique pixel of the package design;
• map the power shape and the signal line to one or more cells in the 3-D array;
• determine if the signal line is a top-side signal line or a bottom-side signal line;
• and
• determine whether the power shape satisfies one of a top-side metal shadowing rule and a bottom-side metal shadowing rule with respect to the signal line.

A computer program product for checking metal coverage in a laminate structure, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

• receive a semiconductor package design comprising a plurality of layers, a power shape, and a signal line;
• compress the plurality of layers into a three-dimensional (3-D) array, wherein each cell of the 3-D array corresponds to a unique pixel of the package design;
• map the power shape and the signal line to one or more cells in the 3-D array;
• determine if the signal line is a top-side signal line or a bottom-side signal line;
• and
• determine whether the power shape satisfies one of a top-side metal shadowing rule and a bottom-side metal shadowing rule with respect to the signal line.