Back to results
US 2019/0377846 A1Published application
Speed converter for fpga-based ufs prototypes
AssigneeSynopsys, Inc.
InventorsRamesh Hanchinal, Sunil Raidurgam Venkat
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeSynopsys, Inc.
InventorsRamesh Hanchinal, Sunil Raidurgam Venkat
Estimating the term…
A method for generating FPGA-based prototype systems capable of implementing UFS HS-G4 communication protocols using inexpensive/slow FPGAs. ASIC/SoC-targeted circuit designs are modified to include a speed converter that causes a UFS controller to generate transmitted data streams at one-half operating speed (e.g., 146 MHz) during HS-G4 operations, modifies the transmitted data streams to intersperse filler data values between transmitted data values, and transmits the modified data streams to M-PHY physical interconnect devices (PIDs) at full speed (e.g., 292 MHz). The speed converter also receives full-speed HS-G4 data streams that include both data and filler values and causes the UFS controller to operate at one-half operating speed (e.g., 146 MHz) such that only data values are read. PLD-based prototype systems that include separate M-PHY PIDs mounted on PCBs are efficiently configured to implement the modified circuit design. A prototyping tool automatically incorporates the speed converters into submitted ASIC/SoC-targeted circuit designs.
A method for prototyping a circuit design including a controller and a physical interconnect layer connected by a standard interface bus and configured to communicate with an external device using a high-speed transmission frequency, the method comprising:
A prototype system for prototyping a circuit design including a Universal Flash Storage (UFS) controller and a M-PHY interconnect layer connected by a standard Reference M-PHY Module Interface (RMMI) bus and configured to communicate with an external device using a High-Speed Gear 4 (HS-G4) transmission frequency, the prototyping system comprising:
A prototyping tool implemented on a computer and utilized to prototype a circuit design including a controller and a physical interconnect layer connected by a standard interface bus and configured to communicate with an external device using a high-speed transmission frequency, the prototyping tool being configured to generate a modified circuit design including a speed converter disposed in the standard interface bus such that the speed converter is coupled to the controller by a first bus portion and to the physical interconnect layer by a second bus portion, wherein the speed converter is configured to convert a first data stream including data values that are received from the controller via the first bus portion at a first frequency into a second data stream including both said data values and one or more filler values that are transmitted to the physical interconnect layer via the second bus portion at a second frequency, wherein the first frequency is less than the second frequency, and wherein said second frequency of said second data stream facilitates re-transmission of said data values and said one or more filler values from said physical interconnect device at said high-speed transmission frequency.
Dependencies are inferred from the claim text.