Dynamic simd instruction issue target selection

A method of data processing comprising:

• performing single instruction multiple data (SIMD) processing in a first data processing cluster comprising a first plurality of data processing lanes, wherein the first plurality of data processing lanes has a first width;
• performing SIMD processing in a second data processing cluster comprising a second plurality of data processing lanes, wherein the second plurality of data processing lanes has a second width;
• issuing decoded instructions to at least one of the first data processing cluster and the second data processing cluster;
• and
• in response to receipt of a decoded SIMD instruction specifying a vector length which is more than the first width:
• issuing a first part of the decoded SIMD instruction having the first width to the first data processing cluster for execution;
• selecting an issuance target for a second part of the decoded SIMD instruction having a remainder width of the vector length less the first width in dependence on a dynamic performance condition,
• wherein when the dynamic performance condition has a first state the issuance target is the first data processing cluster and when the dynamic performance condition has a second state the issuance target is the second data processing cluster;
• and
• scheduling the first and second parts of the decoded SIMD instruction in series when the issuance target is the first data processing cluster.

Apparatus comprising:

• first means for performing single instruction multiple data (SIMD) processing comprising a first plurality of data processing lanes, wherein the first plurality of data processing lanes has a first width;
• second means for performing SIMD processing comprising a second plurality of data processing lanes, wherein the second plurality of data processing lanes has a second width;
• means for issuing decoded instructions to at least one of the first means for performing SIMD processing and the second means for performing SIMD processing;
• and
• in response to receipt of a decoded SIMD instruction specifying a vector length which is more than the first width for causing activation of:
• means for issuing a first part of the decoded SIMD instruction having the first width to the first means for performing SIMD processing for execution;
• means for selecting an issuance target for a second part of the decoded SIMD instruction having a remainder width of the vector length less the first width in dependence on a dynamic performance condition,
• wherein when the dynamic performance condition has a first state the issuance target is the first means for performing SIMD processing and when the dynamic performance condition has a second state the issuance target is the second means for performing SIMD processing;
• and
• means for scheduling the first and second parts of the decoded SIMD instruction in series when the issuance target is the first means for performing SIMD processing.