US 2019/0377697 A1Published application

Microcomputer

AssigneeDenso Corporation

InventorsTatsuya YAMASHITA, Kenji YAMADA

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Abstract

A microcomputer including first and second CPUs is provided. The first and second CPUs may execute identical control programs in parallel. The microcomputer may control a write access by the first or second CPU. The microcomputer may compare an output of the first CPU with an output of the second CPU. Data is written to a write target unit. The microcomputer outputs a write response signal to the first and second CPUs when a data write destination of the first and second CPUs is the write target unit. The microcomputer outputs an abnormality determination signal when data output from the first CPU mismatches with data output from the second CPU. The microcomputer writes the data to the write target unit when the data write destination of the first and second CPUs is the write target unit and the abnormality determination signal is not input.

Claims13

Dependent claims

A microcomputer comprising:

first and second CPUs configured to execute identical control programs in parallel;
a write control unit configured to control a write access by the first or second CPU;
a determination unit configured to compare an output of the first CPU with an output of the second CPU;
and
a write target unit to which data is written by the write control unit, wherein:
the write control unit is configured to output a write response signal to the first and second CPUs before a write to the write target unit is finished when a data write destination of the first and second CPUs is the write target unit;
the determination unit is configured to output an abnormality determination signal to the write control unit when data output from the first CPU mismatches with data output from the second CPU;
and
the write control unit is configured to write the data to the write target unit when the data write destination of the first and second CPUs is the write target unit and the abnormality determination signal is not input to the write control unit.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/549,480Filed 23 Aug 2019
Priority: JP 2017-06284928 Mar 2017
Published: 12 Dec 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 13/38
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units: information…
G06F 9/5027
To service a request: the resource being a machine, e.g. CPUs, Servers, Terminals
G06F 11/1641
Error detection by comparing the output of redundant processing systems: where the comparison is not performed by the redundant processing components
G06F 15/78
Architectures of general purpose stored program computers: comprising a single central processing unit

Family

Application16/549,480Continuation
US 10,733,125 B2Related patent
US 2019/0377697 A1This patent

From the US filing history. Foreign family members aren’t listed.

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