Dynamically adapting mechanism for translation lookaside buffer shootdowns

A method, comprising:

• at an operating system of a processing system comprising a plurality of processor cores, and in response to receiving an indication from a processor core that a mapping of a virtual memory address to a physical memory address is invalid, determining:
• a first cost associated with performing a translation lookaside buffer (TLB) shootdown by sending an inter-processor interrupt to a first subset of the processor cores of the processing system, the first subset comprising processor cores having a TLB that includes one or more entries corresponding to the virtual memory address;
• and
• a second cost associated with performing a TLB shootdown by broadcasting a TLB shootdown signal to each of the processor cores;
• and
• performing the TLB shootdown by sending the inter-processor interrupt to the first subset of processor cores in response to determining that the second cost exceeds the first cost.

A processing system, comprising

• a shared memory;
• a plurality of processor cores, each processor core comprising a translation lookaside buffer (TLB) comprising a plurality of entries indicating mappings of virtual memory address to physical memory addresses;
• and
• an operating system comprising:
• a receiver configured to receive an indication that a first processor core is restricting access to one or more pages of the shared memory;
• a cost calculator configured to determine:
• a first cost for invalidating entries of TLBs corresponding to the one or more pages, the first cost associated with sending an inter-processor interrupt to a first subset of the processor cores of the processing system, the first subset comprising processors comprising a TLB that includes one or more entries corresponding to the one or more pages;
• and
• a second cost for invalidating entries of TLBs, the second cost associated with broadcasting a TLB invalidation signal to processor cores of the processing system;
• and
• a TLB shootdown selector configured to signal the first processor core to send an inter-processor interrupt to the first subset of the processor cores in response to determining that the second cost exceeds the first cost.