Mmio addressing using a translation table

A system for processing an instruction by a processor comprising:

• one or more processors, wherein the one or more processors are operationally connected to one or more buses;
• and
• a memory communicatively coupled to the one or more processors,
• wherein the memory comprises instructions which, when executed by the one or more processors, cause the one or more processors to perform a method comprising:
• determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses;
• determining the address being accessed by the instruction is within the range of MMIO addresses;
• translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus;
• and
• sending, based on the instruction, a request directed to the device via the identified bus to the bus address resulting from the translation.

A computer program product for processing an instruction by a processor, the computer program product comprising a computer readable storage medium having machine executable program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a computer to perform a method comprising:

• determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses;
• determining the address being accessed by the instruction is within the range of MMIO addresses;
• translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus;
• and
• sending, based on the instruction, a request directed to the device via the identified bus to the bus address resulting from the translation.