Extended line width memory-side cache systems and methods

A method for controlling data storage in hierarchical caches implemented between a memory array and processing circuitry, comprising:

• determining a row address and a column address that indicate storage location in the memory array of a first data block targeted by the processing circuitry;
• outputting an activation signal from row select circuitry to a word line coupled to a first memory cell row of the memory array identified by the row address;
• outputting a first column select signal to column select circuitry to enable the memory array to output the first data block from the first memory cell row to a first cache of the hierarchical caches via a first plurality of bit lines each coupled to a first memory cell column of the memory array identified by the column address;
• outputting a first cache line comprising the first data block from the first cache to enable the processing circuitry to perform an operation based at least in part on the first data block;
• and
• outputting a second column select signal to the column select circuitry to enable the memory array to output a second data block from the first memory cell row to the first cache via a second plurality of bit lines each coupled to a second memory cell column different from the first memory cell column while the processing circuitry is performing the operation based at least in part on the first data block.

A computing system comprising a memory sub-system, wherein the memory sub-system comprises:

• one or more memory devices configured to be communicatively coupled to processing circuitry via one or more data buses, wherein the one or more memory devices comprise a first plurality of memory cells organized to form a first memory array corresponding with a first memory channel;
• hierarchical memory caches coupled between the first memory array and the one or more data buses;
• and
• a memory-side memory controller communicatively coupled to the first memory channel and the hierarchical memory caches, wherein the memory-side memory controller is configured to control caching in the hierarchical memory caches of first data blocks stored in the first memory array of the first memory channel based at least in part on a first spatial relationship between first storage locations of the first data blocks in the first memory array.