Arithmetic processing apparatus and control method for arithmetic processing apparatus

A cache memory control process of an arithmetic processing apparatus executed by a cache memory controller, the method comprising:

• perform cache hit judgement based on an address of a memory access instruction;
• issue a memory access request to a memory in a case where the cache hit judgement is a cache miss;
• registering, in response to a speculative first memory access instruction to which a speculative access flag indicating speculative execution and an identification (IID) of a branch instruction are added, data obtained by the memory access request in the cache data memory;
• registering, based on the speculative execution of the speculative access flag, provisional registration information of a provisional registration state indicating that cache registration is performed by execution of a speculative memory access instruction in the cache tag;
• and
• in response to a second memory access instruction issued after the speculative first memory access instruction, to a same address as an address of the speculative first memory access instruction, in a case where the provisional registration information of an entry in the cache tag for which a cache hit occurs has the provisional registration state, judging as a speculative entry cache miss and issuing the memory access request.

An arithmetic processing apparatus comprising:

• an instruction issuer configured to issue an instruction;
• and
• a cache including
• a cache data memory storing a cache tag including a plurality of cache entries, and
• a cache controller configured to
• perform cache hit judgement based on an address of a memory access instruction issued from the instruction issuer, and
• issue a memory access request to a memory in a case where the cache hit judgement is a cache miss,
• wherein the cache controller registers,
• registers in response to a speculative first memory access instruction which is issued from the instruction issuer and to which a speculative access flag indicating speculative execution and an identification (IID) of a branch instruction are added, data obtained by the memory access request in the cache data memory,
• registers, based on the speculative execution of the speculative access flag, provisional registration information of a provisional registration state indicating that cache registration is performed by execution of a speculative memory access instruction in the cache tag, and
• in response to a second memory access instruction issued after the speculative first memory access instruction, to a same address as an address of the speculative first memory access instruction, in a case where the provisional registration information of an entry in the cache tag for which a cache hit occurs has the provisional registration state, judges the second memory access instruction as a speculative entry cache miss and issues the memory access request.