Apparatuses and methods for concurrently accessing different memory planes of a memory

An apparatus, comprising:

• a controller coupled to a memory via a command, address, and data bus, the controller including a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs, wherein the respective information associated with each of the plurality of memory command and address pairs includes a corresponding memory plane identifier of a memory plane of the memory and a corresponding page type identifier that indicates a level of memory cells of the memory being accessed, wherein, using the respective information maintained in the queue, the controller is configured to provide a selected group of memory command and address pairs of the plurality of memory command address pairs to an internal controller of the memory, wherein the controller is configured to use the respective information maintained in the queue to identify individual memory command and address pairs of the plurality of memory command address pairs capable of being concurrently executed by the memory for inclusion in the selected group of memory command and address pairs.