Systems and methods to prevent system crashes due to link failure in memory mirroring mode

An information handling system (IHS), comprising:

• a first memory device;
• a second memory device;
• and
• a processor including an integrated memory controller (IMC), the IMC configured to:
• issue write transactions to both the first memory device and the second memory device when the IMC is in memory mirroring mode;
• issue read transactions to the first memory device when the IMC is in memory mirroring mode;
• and
• transmit a system management interrupt (SMI) with an IMC error to a basic input/output system (BIOS) when a persistent uncorrected IMC error is detected within the first memory device, the processor configured to execute the BIOS to:
• receive the SMI with the IMC error from the IMC;
• and
• perform a memory mirror failover process to cause the IMC to issue the write transactions and the read transactions to the second memory device when the IMC error is a fatal memory link error and the IMC is in memory mirroring mode.