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US 2019/0377634 A1Published application
Memory controller and memory system including the same
AssigneeSK hynix Inc.
InventorYong Il JUNG
Life of this patent
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Abstract
There are provided a memory controller and a memory system including the same. The memory controller includes: a processor for generating a command and an address in response to a request from a host, and generating a bin label and a Log Likelihood Ratio (LLR), based on data received from memory devices; a buffer memory for temporarily storing the data, the bin label, and the LLR; and an error correction circuit for performing error correction decoding on the data, using the LLR.
Claims19
A memory controller comprising:
- a processor configured to generate a command and an address in response to a request from a host, and generate a bin label and a Log Likelihood Ratio (LLR), based on data received from memory devices;
- a buffer memory configured to temporarily store the data, the bin label, and the LLR;
- and
- an error correction circuit configured to perform error correction decoding on the data using the LLR,
- wherein the processor:
- when a result of error correction decoding on data read in a first memory device among the memory devices is determined to have failed, temporarily stores a first bin label of the first memory device in at least one page buffer of the first memory device and then performs error correction decoding for a second memory device;
- when a result of error correction decoding on data read in the second memory device among the memory devices is determined to have failed, temporarily stores a second bin label used in the error correction decoding of the second memory device in at least one page buffer of the second memory device;
- and
- receives the first bin label temporarily stored in the first memory device to perform error correction decoding on data read in the first memory device using another read voltage.
6 more elements
A memory system comprising:
- a first memory device and a second memory device, each of which is configured to store data;
- and
- a memory controller configured to control a read operation of each of the first and second memory devices,
- wherein the memory controller:
- generates a bin label and an LLR based on first data received from the first memory device;
- performs error correction decoding on the first data using the LLR;
- when the error correction decoding fails, transmits the bin label to the first memory device;
- and
- receives second data from the second memory device, and performs error correction decoding on the second data.
6 more elements
A memory system comprising:
- first and second memory devices, each including a memory cell array and at least one page buffer;
- and
- a controller configured to:
- control each the first and second memory devices to repeat an operation of sensing data from the corresponding memory cell arrays and outputting the sensed data to the at least one page buffer, using a different read voltage for each sensing operation, until an error-correction operation is successful;
- generate a bin label based on the sensed data;
- repeat the error-correction operation to the sensed data until the error-correction operation is successful;
- control, during the repeated error-correction operations, each of the first and second memory devices to update the bin label in the at least one page buffer at each failure of the error-correction operation for use at each subsequent error-correction operation,
- wherein the first and second memory devices share a channel and alternately communicate with the controller through the channel.
5 more elements
Dependencies are inferred from the claim text.