Method of equalizing bit error rates of memory device

A resistive type memory device comprising:

• a plurality of banks, each bank comprising a bank row decoder connected to a plurality of word lines of the bank, a bank column decoder connected to a plurality of bit lines of the bank, and a memory cell bank array having memory cells arranged in a plurality of rows and columns, each row of memory cells connected to a corresponding one of the word lines and each column of memory cells being connected to a corresponding one of the bit lines, the memory cells of each bank being organized in a plurality of tiles, each of the memory cells comprising a variable resistor that is programmable to store at least one bit of data;
• an address register configured to provide sequence of memory addresses, each memory address including a bank address identifying one of the plurality of banks, a row address identifying a word line location within the bank identified by the bank address and a column address identifying a subset of bit lines connected to the word line identified by the row address;
• a control circuit configured to provide each row address and column address of each memory address stored by the address register respectively to the bank row decoder and column decoder of the bank identified by the bank address of the corresponding memory address,
• wherein, for at least each memory address of a subset of the memory addresses, the control circuit is configured to modify at least one of the corresponding row address and the corresponding column address such that at least one of the following is true:
• wherein a relative location of a first word line identified by a first row address within a first bank of the plurality of banks is different from a relative location of a second word line identified by the first row address within a second bank of the plurality of banks,
• wherein relative locations of first bit lines identified by a first column address within a first bank of the plurality of banks is different from corresponding relative locations of second bit lines identified by the first column address within a second bank of the plurality of banks, and
• wherein, for the subset of the memory addresses, the control circuit is configured to modify the corresponding column address so that relative locations of the first bit lines identified by the first column address within the first bank of the plurality of banks are different from corresponding relative locations of second bit lines identified by the first column address within the second bank of the plurality of banks.

A method of storing data comprising:

• forming a first codeword from a first block of data;
• storing the first codeword in a resistive type memory device so that a first portion of the first codeword is stored in a first resistive type memory cells of the resistive type memory device and a second portion of the first codeword is stored in second resistive type memory cells of the resistive type memory device, the storing the first codeword in the resistive type memory device comprising:
• sending a write command to the resistive type memory device to store the first codeword in the resistive type memory device,
• sending a first memory address associated with the write command to the resistive type memory device, the memory address including a first row address and a first column address, and
• sending the first codeword to the resistive type memory device,
• wherein the first resistive type memory cells are identified by the first row address and first column address within a first bank of the resistive type memory device,
• wherein the second resistive type memory cells are identified by the first row address and first column address within a second bank of the resistive type memory device, and
• wherein the first resistive type memory cells have a first relative location with respect to the first bank,
• wherein the second resistive type memory cells have a second relative location with respect to the second bank, and
• wherein the first relative location is different from the second relative location.