Dynamic adjustment of issue-to-issue delay between dependent instructions

A system for dynamically adjusting an issue-to-issue delay mode of an instruction sequencing unit, the system comprising:

• at least one processor, wherein the at least one processor comprises an instruction sequencing unit (ISU) that includes:
• first hardware logic configured to:
• initialize the issue-to-issue delay mode to a bypassing mode;
• identify a plurality of instructions in an issue queue;
• and
• determine, for each of the plurality of instructions, whether the instruction is able to issue in the bypassing mode;
• and
• second hardware logic configured to:
• initialize a counter to a predetermined value;
• decrement the counter for each instruction able to issue in the bypassing mode;
• increment the counter for each instruction not able to issue in the bypassing mode;
• determine that the counter is greater than or equal to a threshold value;
• and
• switch the issue-to-issue delay mode to a non-bypassing mode.

A computer program product for dynamically adjusting an issue-to-issue delay mode of an instruction sequencing unit, the computer program product comprising a storage medium readable by a processing circuit, the storage medium storing instructions executable by the processing circuit to cause a method to be performed, the method comprising:

• initializing the issue-to-issue delay mode to a bypassing mode;
• identifying a plurality of instructions in an issue queue;
• determining, for each of the plurality of instructions, whether the instruction is able to issue in the bypassing mode;
• initializing a counter to a predetermined value;
• decrementing the counter for each instruction able to issue in the bypassing mode;
• incrementing the counter for each instruction not able to issue in the bypassing mode;
• determining that the counter is greater than or equal to a threshold value;
• and
• switching the issue-to-issue delay mode to a non-bypassing mode.