Arithmetic processing apparatus and control method for arithmetic processing apparatus

An arithmetic processing apparatus comprising:

• a decoder configured to issue an instruction;
• a first cache memory;
• a second cache memory;
• and
• a processor configured to:
• perform a cache hit determination on the first cache memory in response to a memory access instruction,
• issue a data request to a second cache memory when the cache hit determination is a cache miss,
• wherein when the memory access instruction is a memory access instruction for a speculative execution speculatively executed in a state where a branch destination of a branch instruction is unestablished, the decoder issues the memory access instruction by adding a valid prohibition flag and an instruction identifier of the branch instruction to the memory access instruction, and
• the processor is configured to:
• in a case where the cache hit determination is the cache miss and the prohibition flag of the issued memory access instruction is valid, not issue the data request to the second cache memory, and
• in a case where the cache hit determination is a cache hit, acquire data from the first cache memory and make a response to the memory access instruction.