Adaptive line width cache systems and methods

A method for controlling data storage in hierarchical caches implemented between a memory array and processing circuitry, comprising:

• identifying a first data block that is targeted by the processing circuitry;
• and
• when the first data block results in a processor-side cache miss:
• receiving a first cache line comprising the first data block from a first cache of the hierarchical caches, wherein the first cache line is implemented with a first cache line width;
• storing the first data block in a second cache line implemented in a second cache of the hierarchical caches, wherein the second cache line is implemented with a second cache line width smaller than the first cache line width of the first cache line;
• and
• outputting the second cache line comprising the first data block from the second cache to enable the processing circuitry to begin processing the first data block.

An apparatus comprising a processor, wherein the processor comprises:

• processing circuitry configured to perform an operation based at least in part on a first data block;
• one or more processor-side caches integrated with the processing circuitry;
• and
• a processor-side memory controller integrated with the processing circuitry and the one or more processor-side caches, wherein the processor-side memory controller is configured to:
• determine whether the first data block is currently cached in the one or more processor-side caches;
• and
• when the first data block is not currently cached in the one or more processor-side caches:
• instruct the one or more processor-side caches to store the first data block received via a memory-side cache line in a first processor-side cache line implemented with a line width less than the memory-side cache line;
• and
• instruct the one or more processor-side caches to output the first processor-side cache line comprising the first data block to enable the processing circuitry to begin performing the operation based at least in part on the first data block.

A tangible, non-transitory, computer-readable medium storing instructions executable by one or more processors or a computing system, wherein the instruction comprise instructions to:

• determine, using the one or more processors, a target data block to be used by the one or more processors to perform an operation;
• determine, using the one or more processors, a first storage location of the target data block in a memory array;
• and
• control, using the one or more processors, storage of the target data block and another data block in a plurality of caches hierarchically organized between the memory array and the one or more processors based at least in part on spatial relationship between the first storage location of the target data block and a second storage location of the other data block in the memory array.