Method for performing power saving control in a memory device, associated memory device and memory controller thereof, and associated electronic device

A memory device, comprising:

• a non-volatile (NV) memory, arranged to store information, wherein the NV memory comprises at least one NV memory element;
• and
• a memory controller, coupled to the NV memory, arranged to control operations of the memory device, wherein the memory controller comprises:
• a processing circuit, arranged to control the memory controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the memory controller;
• and
• a transmission interface circuit, coupled to the processing circuit, arranged to perform communications with the host device for the memory device, wherein the transmission interface circuit comprises:
• a physical layer (PHY) circuit, arranged to perform physical layer operations for the transmission interface circuit;
• wherein:
• during transmitting to the host device, the memory controller sends end of burst (EOB)-related symbols to the host device, in order to notify the host device of EOB;
• the memory controller controls the PHY circuit to turn off a clock source within the PHY circuit, in order to save power;
• and
• when receiving a trigger signal from the host device, the PHY circuit turns on the clock source.

A memory controller of a memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the memory controller comprising:

• a processing circuit, arranged to control the memory controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the memory controller;
• and
• a transmission interface circuit, coupled to the processing circuit, arranged to perform communications with the host device for the memory device, wherein the transmission interface circuit comprises:
• a physical layer (PHY) circuit, arranged to perform physical layer operations for the transmission interface circuit;
• wherein:
• during transmitting to the host device, the memory controller sends end of burst (EOB)-related symbols to the host device, in order to notify the host device of EOB;
• the memory controller controls the PHY circuit to turn off a clock source within the PHY circuit, in order to save power;
• and
• when receiving a trigger signal from the host device, the PHY circuit turns on the clock source.