Low latency combined clock data recovery logic network and charge pump circuit

An apparatus comprising:

• one or more samplers configured to operate on a received input signal according to a sampling clock, the one or more samplers further configured to generate a sequence of data decisions obtained from a history buffer and an error signal;
• a set of logic branches, each logic branch receiving the sequence of data decisions and the error signal, each logic branch from the set of logic branches configured to be selected in accordance with the sequence of data decisions and the error signal responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch configured to generate an output current;
• and
• a local oscillator controller configured to receive the output current and to adjust an input voltage of a proportional control circuit, the output current sourcing and sinking current to a capacitor through a resistive element to adjust the input voltage of the proportional control circuit relative to a voltage on the capacitor connected to the resistive element.