Chromeless Phase Shift Mask Structure and Process

A mask, comprising:

• a transparent substrate having a first region and a second region being adjacent the first region;
• a material layer substantially transparent and disposed over the transparent substrate and patterned to form a transparent feature within the first region and an opening within the second region;
• and
• an etch stop layer interposed between the material layer and the transparent substrate, wherein the etch stop layer includes at least one of ruthenium oxide, tungsten nitride, and titanium nitride and is doped with at least one of phosphorous (P), calcium (Ca), and sodium (Na), and continuously extends from the first region to the second region.

A method for integrated circuit fabrication, comprising:

• providing a semiconductor substrate;
• providing a photoresist layer over the semiconductor substrate;
• providing a mask that includes
• a substrate;
• an etch stop layer disposed on the substrate, wherein the etch stop layer includes at least one of ruthenium oxide, tungsten nitride, and titanium nitride and is doped with at least one of phosphorous (P), calcium (Ca), and sodium (Na);
• and
• a material layer substantially transparent to a light radiation and disposed on the etch stop layer and patterned according to an integrated circuit pattern;
• and
• forming the integrated circuit pattern on the semiconductor substrate by utilizing the mask in a lithography process including
• performing a lithography exposure process to the semiconductor substrate utilizing the mask;
• and
• developing the exposed photoresist layer.