US 2019/0377234 A1 · DISPLAY PANEL

Abstract

A display panel has an odd-shaped active area and a peripheral area. The display panel includes a substrate, pixel units, gate lines and at least one dummy thin film transistor. The pixel units are disposed on the active area of the substrate. The gate lines are disposed on the substrate, each of the gate lines is coupled to one or more of the pixel units, and the number of pixel units coupled to a first gate line of the gate lines is smaller than the number of pixel units a second gate line coupled to of the gate lines. The dummy thin film transistor is disposed on the substrate, and is coupled to the first gate line.

Claims12

Dependent claims

A display panel having an active area that is odd-shaped and a peripheral area, the display panel comprising:

a substrate;
a plurality of pixel units disposed on the substrate and in the active area;
a plurality of gate lines disposed on the substrate, each of the gate lines coupled to one or more of the pixel units, and the number of pixel units coupled to a first gate line of the gate lines is smaller than the number of pixel units coupled to a second gate line of the gate lines;
and
at least one dummy thin film transistor disposed on the substrate and coupled to the first gate line.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/431,712Filed 4 Jun 2019

Priority

CN 201810573350.56 Jun 2018

Published

12 Dec 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

G02F 1/136286
Active matrix addressed cells: wiring, e.g. gate line, drain line
G02F 1/1368
Active matrix addressed cells: in which the switching element is a three-electrode device
H10D 86/411
Characterised by multiple TFTs: characterised by materials, geometry or structure of the substrates
H10D 86/441
Characterised by multiple TFTs: interconnections, e.g. scanning lines

Display panel

Life of this patent

Display panel

Life of this patent

Abstract

Claims12