Phase preset for fast chirp pll

A method for presetting a phase of a fast chirp Phase Locked Loop, PLL, comprising:

• generating a Frequency Modulated Continuous Waveform, FMCW, with a Voltage Controlled Oscillator, VCO, the VCO responding to a filtered output voltage;
• dividing the FMCW, with a frequency divider, to generate a divided frequency waveform;
• generating a charge pump voltage in response to a difference between a reference frequency waveform and the divided frequency waveform;
• filtering the charge pump voltage with a filter, to generate the filtered output voltage;
• modifying, with a digital controller, a division ratio of the frequency divider to generate a chirp phase and a return phase, the chirp phase including a first linear change of the FMCW from a start frequency to a stop frequency, and the return phase including a second linear change of the FMCW from the stop frequency to the start frequency;
• and
• supplying, with a phase preset circuit, a phase preset current to the filter during a start frequency time preceding the chirp phase, wherein the phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

A method for presetting a phase of a fast chirp Phase Locked Loop, PLL, comprising:

• generating a Frequency Modulated Continuous Waveform, FMCW, with the PLL, the PLL including a low pass filter configured to generate a filtered output voltage by filtering a charge pump voltage of a charge pump, the charge pump responsive to a difference between a divided FMCW and a reference frequency waveform, the FMCW including a chirp phase and a return phase, the chirp phase including a first linear change of the FMCW from a start frequency to a stop frequency, and the return phase including a second linear change of the FMCW from the stop frequency to the start frequency;
• and
• supplying a phase preset current to the low pass filter during a start frequency time preceding the chirp phase, wherein determining the phase preset current comprises:
• measuring a start voltage from the filtered output voltage while an FMCW frequency is equal to the start frequency,
• setting the FMCW frequency to the stop frequency, wherein the filtered output voltage equals a stop voltage,
• disabling the charge pump, supplying a calibration current to the low pass filter, and counting a number of clock cycles elapsed during a change from the stop voltage to the start voltage, wherein each clock cycle has a clock period,
• setting the phase preset current equal to the calibration current multiplied by the number of clock cycles, multiplied by the clock period, and divided by a duration of the chirp phase, and
• enabling the charge pump, and supplying the phase preset current during a subsequent start frequency time.