Image sensor with s/h-to-adc voltage range matching
AssigneeSony Semiconductor Solutions Corporation
InventorsNoam Eshel, Golan Zeituni
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Abstract
An image sensor comprises a plurality of image pixel circuits arranged in an array; image processing circuitry including a sample-and-hold circuit configured to receive a first reference voltage and an analog-to-digital converter configured to receive a second reference voltage; and a reference adjustment circuit configured to selectively adjust the first reference voltage and/or the second reference voltage, thereby to match an operating range of the sample-and-hold circuit with an operating range of the analog-to-digital converter, based on a measurement signal.
Claims20
An image sensor, comprising:
- a plurality of image pixel circuits arranged in an array;
- image processing circuitry including a sample-and-hold circuit configured to receive a first reference voltage and an analog-to-digital converter configured to receive a second reference voltage;
- and
- a reference adjustment circuit configured to selectively adjust the first reference voltage and/or the second reference voltage, thereby to match an operating range of the sample-and-hold circuit with an operating range of the analog-to-digital converter, based on a measurement signal.
A method of operating an image sensor that comprises a plurality of image pixel circuits arranged in an array, image processing circuitry including a sample-and-hold circuit and an analog-to-digital converter, and a reference adjustment circuit, the method comprising:
- receiving, by the sample-and-hold circuit, a first reference voltage;
- receiving, by the analog-to-digital converter, a second reference voltage;
- and
- selectively adjusting, by the reference adjustment circuit, the first reference voltage and/or the second reference voltage, thereby to match an operating range of the sample-and-hold circuit with an operating range of the analog-to-digital converter, based on a measurement signal.
An image sensor, comprising:
- a plurality of image pixel circuits arranged in a first array having M rows and N1 columns, wherein M and N1 are positive integers;
- a plurality of dummy pixel circuits arranged in a second array having M rows and N2 columns, wherein N2 is a positive integer;
- image processing circuitry including a sample-and-hold circuit configured to receive a first reference voltage and an analog-to-digital converter configured to receive a second reference voltage;
- and
- a reference adjustment circuit configured to selectively adjust the first reference voltage and/or the second reference voltage, thereby to match an operating range of the sample-and-hold circuit with an operating range of the analog-to-digital converter, based on a measurement signal.
Dependencies are inferred from the claim text.