Sample-and-hold circuit with feedback and noise integration

A method of reducing a noise in a sample-and-hold circuit including a sampling capacitor, and amplifier transistor, and a noise reduction circuit, the method comprising:

• discharging a feedback capacitor of the noise reduction circuit;
• partially compensating a gate voltage of the amplifier transistor through the feedback capacitor;
• charging the integration capacitor;
• and
• fully compensating the gate voltage of the amplifier transistor by a voltage on the integration capacitor through the feedback capacitor.

An image sensor, comprising:

• a plurality of pixel circuits arranged in an array;
• a sample-and-hold circuit;
• and
• an analog-to-digital converter configured to receive an output from the sample-and-hold circuit,
• wherein the sample-and-hold circuit includes a sampling capacitor, an amplifier transistor, and a noise reduction circuit having an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including:
• an auto-zero phase in which the feedback capacitor is discharged,
• a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor,
• an integration phase in which the integration capacitor is charged, and
• a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.