Fast termination of multilane double data rate transactions

An apparatus, comprising:

• a bus interface configured to couple the apparatus to a multilane serial bus;
• and
• a processor configured to:
• provide a data payload for a data frame to be transmitted over a plurality of data lanes of the multilane serial bus;
• provide a preamble to precede the data payload in transmission over the multilane serial bus;
• configure one or more repurposed bit fields in the data frame to indicate that a multi-bit cyclic redundancy check is provided in the data frame;
• and
• transmit the data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus,
• wherein at least one bit of the multi-bit cyclic redundancy check is transmitted on each of two or more data lanes of the plurality of data lanes.

An apparatus, comprising:

• means for providing a data payload for a data frame to be transmitted over a plurality of data lanes of a multilane serial bus;
• means for providing a preamble to precede the data payload in transmission over the multilane serial bus;
• means for configuring one or more repurposed bit fields in the data frame to indicate that a multi-bit cyclic redundancy check is provided in the data frame;
• and
• means for transmitting the data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus,
• wherein at least one bit of the multi-bit cyclic redundancy check is transmitted on each of two or more data lanes of the plurality of data lanes.

A processor-readable storage medium comprising code for:

• providing a data payload for a data frame to be transmitted over a plurality of data lanes of a multilane serial bus;
• providing a preamble to precede the data payload in transmission over the multilane serial bus;
• configuring one or more repurposed bit fields in the data frame to indicate that a multi-bit cyclic redundancy check is provided in the data frame;
• and
• transmitting the data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus,
• wherein at least one bit of the multi-bit cyclic redundancy check is transmitted on each of two or more data lanes of the plurality of data lanes.