Comparator offset voltage self-correction circuit

A comparator offset voltage self-correction circuit, comprising:

• a multiplexer, an offset digital adjustment amplifier, a dynamic comparator, a successive approximation register, an analog signal input port Vin, a correction signal input port Vcal, a reference signal input port Vr, a clock port, an enable port and an output port, wherein the analog signal input port Vin is configured to receive an analog signal;
• the correction signal input port Vcal is configured to receive a correction signal;
• the reference signal input port Vr is configured to receive a reference signal;
• the clock port is configured to receive an input clock signal;
• the enable port is configured to start a correction process;
• the output port is configured to output a comparison result;
• a first selection end of the multiplexer is connected to the correction signal input port Vcal, a second selection end of the multiplexer is connected to the analog signal input port Vin, and an output end of the multiplexer is connected to a non-inverting input end VP of the offset digital adjustment amplifier;
• an inverting input end VM of the offset digital adjustment amplifier is connected to the reference signal input port Vr;
• a non-inverting output end VOP of the offset digital adjustment amplifier is connected to a non-inverting input end VP of the dynamic comparator;
• an inverting output end VOM of the offset digital adjustment amplifier is connected to an inverting input end VM of the dynamic comparator;
• an output end of the dynamic comparator is connected to the output port;
• digital output ends D0, D1, D2, D3, D4, D5, D6 and D7 of the successive approximation register are connected to digital input ends D0, D1, D2, D3, D4, D5, D6 and D7 of the offset digital adjustment amplifier, an enable end of the successive approximation register is connected to the enable port, a clock end of the successive approximation register is connected to the clock input port, and a data end Din of the successive approximation register is connected to an output end of the dynamic comparator;
• the clock input port is connected to the clock ends of both the successive approximation register and the dynamic comparator;
• and an equivalent input offset of the offset digital adjustment amplifier is
• V
• io
• =
• -
• 2
• 
• c
• g
• m
• 
• R
• 141
• 
• (
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• +
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• =
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• i
• +
• c
• g
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• ,
• wherein c is a constant, gm represents a transconductance coefficient of the offset digital adjustment amplifier, R141 represents a resistance value of a resistor, and R143 represents a resistance value of a resistor.