PLL with Beat-Frequency Operation

A second beat-frequency PLL, comprising:

• a controlled oscillator with an output clock frequency;
• a modulo-K counter with a first K value related to a first bit width and a second K value related to a second bit width, wherein a modulo-K counter input is coupled with a controlled oscillator output;
• a phase predictor with the first K value, the first bit width, a first frequency control word (first FCW), the second K value, the second bit width, and a second FCW;
• and
• a lock detector configured to provide a phase lock indicator signal;
• wherein, upon the phase lock indicator signal indicating that the second beat-frequency PLL is in lock, at a start of a modulo-K counter modulo-K cycle, the modulo-K counter switches from the first K value and the first bit width to the second K value and the second bit width, and the phase predictor simultaneously switches from the first K value, the first bit width and the first FCW to the second K value, the second bit width, and the second FCW.

A method for operating a beat-frequency PLL, comprising the following steps:

• determining multiple frequency lock ranges (multiple FLRs) covering a controlled oscillator frequency range;
• based on a required frequency, determining a target FLR, wherein the target FLR is one of the multiple FLRs and the target FLR includes the required frequency;
• operating the controlled oscillator at a frequency in the target FLR;
• determining a final K-value related to the multiple FLRs and a final FCW to generate the required frequency in the target FLR;
• and
• simultaneously setting the final K-value and the final FCW at a start of a modulo-K counter modulo-K cycle and operating the beat-frequency PLL to generate the required frequency in the target FLR.