Injection locked frequency divider

An injection locked frequency divider, comprising:

• a signal injection circuit including
• an injection transistor having a gate terminal that is disposed to receive an input voltage signal having an input frequency, a drain terminal, a source terminal that cooperates with said drain terminal to provide a first differential signal pair, and a body terminal, and
• a resistor coupling said body terminal of said injection transistor to a biasing voltage source, and configured to make a voltage at said body terminal of said injection transistor higher than a voltage at said source terminal of said injection transistor;
• and
• an oscillating circuit coupled to said signal injection circuit, and configured to cooperate with said signal injection circuit to define a free-running frequency and a frequency locking range which is around N times the free-running frequency, such that the input frequency falls within the frequency locking range, where N is a positive integer not smaller than two;
• wherein said oscillating circuit cooperates with said signal injection circuit to generate a second differential signal pair that is related to the first differential signal pair and that has an oscillating frequency which is one-Nth the input frequency.