US 2019/0356316 A1 · TECHNOLOGY MAPPING METHOD OF AN FPGA

Abstract

A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.

Claims10

Dependent claims

A technology mapping method for a FPGA, comprising:

converting a gate level netlist into an AND-Inverter Graph (AIG) netlist;
selecting a node among nodes included in the AIG netlist;
generating a cut set including one or more cuts corresponding to the selected node;
selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria;
and
outputting a LUT netlist including the best cut,
wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/529,669Filed 1 Aug 2019

Priority

KR 10-2017-003899428 Mar 2017

Published

21 Nov 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H03K 19/1776
Structural details of configuration resources: for memories
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/343
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: logical level

Technology mapping method of an fpga

Life of this patent

Technology mapping method of an fpga

Life of this patent

Abstract

Claims10