Reducing glitches that occur when multiplexing of asynchronous clocks using flip-flops and logic gates

A method comprising:

• receiving, at an enable terminal of a first flip-flop, an output of a first combinational logic, wherein one or more inputs of the first combinational logic comprises a disable first clock signal from a clock switchover circuit and a disable second clock signal from the clock switchover circuit;
• receiving, at a set terminal of the first flip-flop, an output of a logic gate, wherein the logic gate receives a select signal and a first clock stopped signal, the first clock stopped signal indicating a stop in the first clock signal;
• receiving, at an input terminal of the first flip-flop, an output of a second flip-flop;
• receiving, at a reset terminal of the first flip-flop, an output of a second combinational logic, wherein one or more inputs of the second combinational logic comprise the first clock stopped signal, a power-on-reset signal, and the select signal;
• and
• outputting, at an output terminal of the first flip-flop, a modified select signal.