US 2019/0356309 A1Published application

Switch circuit

AssigneeMurata Manufacturing Co., Ltd.

InventorToshio SUDA

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Abstract

A switch circuit includes FETs including a first FET group including m FETs, a second FET group including n FETs at a position away from the input terminal than the first FET group, and an intermediate FET between the first FET group and the second FET group, and capacitive elements including m capacitive elements, n capacitive elements, and an intermediate capacitive element, the capacitive element (C1i) (i is an integer between 1 and m inclusive) is connected in parallel to i consecutive FETs of the first FET group starting from a top closer to the input terminal, the capacitive element (C2j) (j is an integer between 1 and n inclusive) is connected in parallel to j consecutive FETs of the second FET group starting from a top closer to the input terminal, and the intermediate capacitive element is connected in parallel to the intermediate FET.

Claims15

Dependent claims

A switch circuit comprising:

an input terminal to which a signal is inputted;
an output terminal from which the signal is outputted;
a plurality of FETs that is multistage-connected between the input terminal and the output terminal, wherein an on and off state of each FET of the plurality of FETs is controlled in response to a control voltage supplied to a gate of each FET of the plurality of FETs;
and
a plurality of capacitive elements, wherein
the plurality of FETs includes
a first FET group including m adjacent FETs, the m being an integer equal to or more than two,
a second FET group including n adjacent FETs, the n being an integer equal to or more than two, the second FET group being provided at a position farther away from the input terminal than the first FET group, and
an intermediate FET connected between the first FET group and the second FET group,
the plurality of capacitive elements including:
m capacitive elements including capacitive elements C11, C12, . . . , C1m,
n capacitive elements including capacitive elements C21, C22, . . . , C2n, and
an intermediate capacitive element,
a capacitive element C1i is connected in parallel to i consecutive FETs of the first FET group starting from a top closer to the input terminal, the i being an integer between 1 and m inclusive,
a capacitive element C2j is connected in parallel to j consecutive FETs of the second FET group starting from a top closer to the input terminal, the j being an integer between 1 and n inclusive, and
the intermediate capacitive element is connected in parallel to the intermediate FET.

13 more elements

A switch circuit comprising:

an input terminal to which a signal is inputted;
an output terminal from which the signal is outputted;
a plurality of FETs that is multistage-connected between the input terminal and the output terminal, wherein an on and off state of each FET of the plurality of FETs is controlled in response to a control voltage supplied to a gate of each FET of the plurality of FETs;
and
a plurality of capacitive elements, wherein
the plurality of FETs includes
a first FET group including m adjacent FETs, the m being an integer equal to or more than two,
a second FET group including n adjacent FETs, the n being an integer equal to or more than two, the second FET group being provided at a position farther away from the input terminal than the first FET group,
a third FET group including 1 adjacent FETs, the l being an integer equal to or more than two, the third FET group being provided at a position farther away from the input terminal than the second FET group,
a first intermediate FET connected between the first FET group and the second FET group, and
a second intermediate FET connected between the second FET group and the third FET group,
the plurality of capacitive elements including:
m capacitive elements including capacitive elements C11, C12, . . . C1m,
n capacitive elements including capacitive elements C21, C22, . . . C2n,
l capacitive elements including capacitive elements C21, C22, . . . C2l,
a first intermediate capacitive element, and
a second intermediate capacitive element,
a capacitive element C1i is connected in parallel to i consecutive FETs of the first FET group starting from a top closer to the input terminal, the i being an integer between 1 and m inclusive,
a capacitive element C2j is connected in parallel to j consecutive FETs of the second FET group starting from a top closer to the input terminal, the j being an integer between 1 and n inclusive,
a capacitive element C3k is connected in parallel to k consecutive FETs of the second FET group starting from a top closer to the input terminal, the k being an integer between 1 and l inclusive,
the first intermediate capacitive element is connected in parallel to the first intermediate FET, and
the second intermediate capacitive element is connected in parallel to the second intermediate FET.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/529,936Filed 2 Aug 2019
Priority: JP 2017-0214098 Feb 2017
Published: 21 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03K 17/687
By the use, as active elements, of semiconductor devices: the devices being field-effect transistors
H01P 1/15
For switching or interrupting: by semiconductor devices
H03K 17/102
Modifications for increasing the maximum permissible switched voltage: in field-effect transistor switches
H03K 17/6871
The devices being field-effect transistors: the output circuit comprising more than one controlled field-effect transistor

Family

Application16/529,936Continuation
US 10,826,490 B2Related patent
US 2019/0356309 A1This patent

From the US filing history. Foreign family members aren’t listed.

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